mv1820 6 internet: http://www.gpsemi.com customer service centres france & benelux les ulis cedex tel: (1) 69 18 90 00 fax : (1) 64 46 06 07 germany munich tel: (089) 419508-20 fax : (089) 419508-55 italy milan tel: (02) 6607151 fax: (02) 66040993 japan tokyo tel: (03) 5276-5501 fax: (03) 5276-5510 korea seoul tel: (2) 5668141 fax: (2) 5697933 north america scotts valley, usa tel: (408) 438 2900 fax: (408) 438 5576/6231 south east asia singapore tel:(65) 3827708 fax: (65) 3828872 sweden stockholm tel: 46 8 702 97 70 fax: 46 8 640 47 36 taiwan, roc taipei tel: 886 2 25461260 fax: 886 2 27190260 uk, eire, denmark, finland & norway swindon tel: (01793) 726666 fax : (01793) 518582 these are supported by agents and distributors in major countries world-wide. ?mitel corporation 1998 publication no. ds3106 issue no. 3.0 may 1996 technical documentation ?not for resale. printed in united kingdom headquarters operations mitel semiconductor cheney manor, swindon, wiltshire sn2 2qw, united kingdom. tel: (01793) 518000 fax: (01793) 518411 mitel semiconductor 1500 green hills road, scotts valley, california 95066-4922 united states of america. tel (408) 438 2900 fax: (408) 438 5576/6231 this publication is issued to provide information only which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. no warranty or guarantee express or implied is made regard ing the capability, performance or suitability of any product or service. the company reserves the right to alter without prior notice the specification, design or price of any product or service. information con cerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user's responsibility to f ully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to the company's conditions of sale, w hich are available on request. all brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respec tive owners. purchase of mitel semiconductor i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
mv1820 5
mv1820 4 crystal specification parallel resonant fundamental frequency 27.750000mhz. at cut. nominal load capacitance 20pf. tolerance at -10 c to 60 c 50ppm. equivalent series resistance <20 ? . tolerance overall 100ppm. functional description the video signal is sliced to produce data and synchronising signals. timing circuits monitor the sync signal to enable the mv1820 to lock onto the broadcast signal. a timing window, for the vertical blanking interval (vbi) lines 6 - 22 and 318 - 335, is established to enable the acquisition circuit to monitor the sliced data signal for valid teletext data. the framing code is checked for valid world system teletext (wst) data. magazine, packet and designation code bytes are checked and valid broadcast service data packets (bsdp) format two type only are accepted. these are known as packet 8/30. format two is signalled by byte six, data bit two being set high and bits 3 and 4 set low. bytes 13 to 25 inclusive are hamming decoded (8,4) and stored in seven registers each of eight bits. if the complete message is correctly received with no uncorrectable hamming errors, an interrupt to the microprocessor is signalled by the dav (bar) pin going low. at the same time the data is transferred to a second bank of registers, reorganised with original numbered bytes 14, 15, 24, 25 and 13 placed after byte 23, to be read out on the i 2 c bus when so requested. subsequent valid messages will continue to be transferred to the output registers overwriting any existing data. in this way the output registers always contain the latest pdc message. the mv1820 is configured as an i 2 c bus slave transmitter with a selectable address. the i 2 c bus address is 0010 0001 (20 + 1 hex) with the address select (as) pin set high, or 0010 0011 (22 + 1 hex) with the as pin set low. the read bit (lsb) must always be set, it is not possible to write to the mv1820. on recognising its address, the mv1820 will send an acknowledge and then transmit on the sda line the first byte from the output registers (decoded byte 16 and 17) most significant bit (msb) first. it will then monitor the sda line for an acknowledge from the microprocessor. if the microprocessor does not send an acknowledge, the mv1820 will release the data line to allow the microprocessor to send a stop condition. if the microprocessor does send an acknowledge, the following bytes of the message will be output provided each byte is acknowledged. the final data will be byte 13 followed by the four 1 s. when readout is complete, the dav (bar) pin is reset high and the output registers are all set high. if the microprocessor continues to send clocks on the scl line, the mv1820 will output ff bytes on the sda line. also, if the mv1820 is re- addressed before another pdc message is received, the mv1820 will output ff bytes on the sda line. the microprocessor can prematurely stop the message by not sending an acknowledge followed by a stop condition after any byte has been sent by the mv1820. the registers will then be reset to ff bytes and the dav pin will be reset high. to prevent any corruption of the data in the output registers during i 2 c bus activity, valid pdc messages are held in the incoming registers until i 2 c bus activity ceases. here they may be overwritten by new pdc messages until the i 2 c bus activity ceases and they can then be transferred to the output registers. system clock is provided by an on - chip 27.75mhz oscillator together with an external parallel resonant fundamental frequency at cut crystal. following a reset, reset pulled low, the output i 2 c bus registers will contain ff bytes and the dav pin will be set high. when the power supply is removed, the i 2 c bus will not be clamped to ground, leaving it free for other i 2 c bus traffic. fig.3 typical application diagram
mv1820 3 electrical characteristics (continued) these characteristics are guaranteed over the following conditions (unless otherwise stated) t amb = 0 to 70?c, v dd = 5v 10% i2c bus scl, sda schmitt inputs input voltage low input voltage high output voltage low scl clock frequency dav data available output voltage low reset schmitt input input voltage low input voltage high input current low input current high 11, 13 11 1 0 3.5 0 v dd -1.0 -22 -10 0.1 100 0.2 -50 1.5 v dd 0.4 1000 0.4 0.8 v dd -220 +10 v v v khz v v v a a not clamped when v dd = 0v i ol = 3.0ma 100k (nom) pull-up resistor i oh = 2.4ma 100k (nom) pull-up resistor v in = v ss v in = v dd characteristic pin min typ max value units conditions note input voltage low and input voltage high for ext/int, as and xti are as specified for data i/o. as xto xti pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pin name and description active low reset. includes a 100k ? pull - up resistor control pin for sync i/o and data i/o. includes a 100k ? pull - down resistor. when low or not connected, internal sync and data are used, pins 9 and 10 are outputs. when high, supply sync and data from an external source, pins 9 and 10 are inputs. black level capacitor. white level capacitor. input for composite video signal with negative going syncs ground 0 volts. time constant resistor. controlling discharge rate of black and white level capacitor voltages. address select for i 2 c bus. [0010 0001] with as set high, or [0010 0011] with as set low. includes 100k ? pull - down resistor. data input/output. sync input/output. i 2 c bus serial clock. positive supply voltage +5v 10% i 2 c bus bi-directional data port. active low open drain output data available signal to microprocessor. includes 100k ? pull - up resistor crystal out, 27.75mhz fundamental crystal with on-chip 1m ? resistor to xti. crystal input. data i/o sync i/o scl vdd sda dav pin description symbol reset ext/int blc wlc video gnd tcr
mv1820 2 electrical characteristics these characteristics are guaranteed over the following conditions (unless otherwise stated) t amb = 0 to 70?c, v dd = 5v 10% supply voltage supply current video input video amplitude source impedance tcr input external resistance blc and wlc capacitor value capacitor tolerance effective series resistance data i/o and sync i/o output voltage high output voltage low input voltage low input voltage high input current ext/int input voltage low input voltage high input current low input current high as input voltage low input voltage high input current low input current high xti input input current low input current high xto output output voltage high output voltage low frequency 12 12 5 7 3 & 4 9 & 10 2 8 16 15 4.5 0.8 4.7 -10% v dd -1.0 0 v dd -1.0 -30 0 v dd -1.0 -10 22 0 v dd -1.0 -10 22 -0.5 0.5 v dd -1.0 5.0 20 1.8 4.7 10 4.5 0.2 50 50 -5.0 5.0 4.5 0.2 27.750 5.5 25 3.0 250 200 +10% 5 0.4 0.8 v dd +30 0.8 v dd +10 220 1.0 v dd +10 220 -20 20 0.4 v ma vpp ? k ? nf ? v v v v a v v a a v v a a a a v v mhz bottom of sync to white (pk to pk) connected to v dd connected to gnd 1mhz i oh = -1.2ma i ol = 2.4ma v in = v ss or v dd 100k (nom) pull-down resistor v in = v ss v in = v dd 100k (nom) pull-down resistor v in = v ss v in = v dd -0.3 the mv1820 is a high speed cmos receiver for programme delivery control (pdc) messages broadcast in world system teletext (wst) format two broadcast service data packets (bsdp). the pdc message can be read on an i 2 c bus with data format similar to standard video programming service (vps) decoders. additional data is appended to include new pdc features. it is intended for use in video cassette recorders to provide automatic recording of suitably labelled television programmes requested by the user. features on chip data slicing low external component count i 2 c bus for low cost interfacing advanced cmos technology gives low power dissipation and high reliability absolute maximum ratings supply voltage 0.3v to 7v all inputs -0.3 to v dd +0.3v operating temperature 0 to +70 c storage temperature -55 to 125 c ordering information mv1820f/cg/dpas mv1820f/cg/mpes pin 1 2 3 4 5 6 7 8 pin 16 15 14 13 12 11 10 9 description xti xto dav sda vdd scl sync i/o data i/o description reset ext/int blc wlc video gnd tcr as 7 10 6 11 5 12 4 13 3 14 2 15 1 16 8 7654321 8 9 10 11 12 13 14 15 16 9 dp16 mp16 fig.1 pin connections - top view fig.2 mv1820 block diagram supersedes version in october 1995 media ic handbook, hb3120 - 3.0 ds3106 - 3.0 may 1996 mv1820 video programme delivery control interface circuit
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